Non-volatile semiconductor or solid-state memories have the advantage of being fast, light-weight and low-power. Examples are ROM (read only memory), PROM (programmable read only memory), and EEPROM (electrically erasable programmable read only memory), which retain their memory even after power is shut down. However, ROM and PROM cannot be reprogrammed. EEPROM's have the advantage of being electrically writable (or programmable) and erasable. EEPROMs are used in electronic devices for storage of essential information which has to be maintained during power off and/or which has to be available when the electronic system is initialized. These semiconductor memories have been employed in small amounts for permanent storage of certain computer system codes or system parameters that do not change.
One common application of the use of an EEPROM is in network interface cards, such as those of the Next Generation Input/Output (NGIO) network interface card. In the interface cards, a controller needs access to non-volatile information which is established at the time of the board manufacturing. Examples of this non-volatile information includes a globally unique identification (GUID), the size of an external FLASH (if any), the subsystem vendor, the device identifications, and the configuration of the ports. The EEPROM can be programmed to store this information.
Board manufactures can generally choose what size EEPROM to include for each application. However, to access the information on the EEPROM, the controller on the board needs information on the size of the EEPROM. The size of the EEPROM has previously been communicated with the use of software or dedicated strapping pins. Each of these solutions increased the complexity of the boards and the cost of manufacturing, and did not allow the board designer to easily adjust the size of the EEPROM.
A system to provide flexibility in part selection for an interface card is desirable. This would allow various sizes of EEPROMS to be used with a controller, allowing the designer to minimize the number of interfaces supported. Additionally, if the size of the EEPROM was easily determined, the designer could select the least expensive EEPROM available.